Separately, semiconductor design tool market leaders Cadence Design Systems Inc and Synopsys Inc both announced 45-nm reference flows targeting Common Platform technology available for general release in July 2008.

To address advanced node design requirements, Cadence said it worked with the Common Platform technology companies -- IBM, Chartered Semiconductor Manufacturing and Samsung Electronics – on its RTL to GDSII 45-nm flow, which is based on the Common Power Format (CPF)-enabled Cadence low-power technology and also includes key design for manufacturing (DFM) technology from Cadence.

Cadence said it expects this flow to provide power savings, yield enhancement and time-to-market advantages for customers designing high-volume consumer, communications and mobile electronic devices targeted to the Common Platform technology 45-nm process.

This reference flow uses ARM’s 45-nm physical IP low-power libraries to allow designers to perform design exploration and physical prototyping using different CPF files and a single golden RTL, and to allow low-power architecture optimization by employing the advanced power management capabilities in Cadence’s low power software products including power shut off prototyping, power domain-aware placement, clock tree synthesis and routing, multi-mode and multi-corner analysis and optimization, meant to deliver higher productivity and the utmost in power reduction for advanced designs.

As part of this reference flow, Cadence said it is also providing an integrated suite of foundry certified, model-based DFM analysis and implementation technologies for silicon-accurate analysis and physical design optimization that offer silicon-accurate modeling and optimization of critical manufacturing variations that can be used to improve both performance and physical yield results during design implementation.

At advanced process nodes, traditional design flows no longer provide accurate predictability, forcing designers to either guardband their designs excessively or risk manufacturability problems. By modeling key manufacturing processes within the implementation flow and optimizing early, designers reduce overall turnaround time and improve their confidence that the chip will work as intended, Cadence reminded.

Cadence’s 45-nm reference flow is built around the company’s Encounter platform for DFM-aware prevention, detection and optimization and has been demonstrated within the Common Platform that features which may result in yield-limiting issues in lithography are quickly and accurately identified using the Cadence Litho Physical Analyzer.

The results are then used to drive the Cadence SoC Encounter RTL-to-GDSII system -- for prevention and manufacturing-aware design closure, and Cadence Chip Optimizer -- for incremental space-based interconnect optimization and final manufacturability optimization. Next, Cadence said its QRC Extractor provides a modeling link between the physical, manufacturing and electrical domains whereby DFM effects can be extracted and timing impact can be back-annotated to the physical implementation stage for accurate model-based timing optimization.

In the case of Synopsys, its 45-nm RTL-to-GDSII low power Common Platform reference design flow was derived from the company’s Pilot Design Environment, and aims to be a comprehensive design implementation methodology to allow SoC development teams to reduce power and cost while improving performance when designing with the Common Platform technology 45-nm process.

Synopsys noted that its reference flow is built around the company’s Eclypse low power technology that incorporates the Galaxy design platform implementation and signoff tools and the Unified Power Format (UPF) language, using the latest technology files from the Common Platform foundries and ARM Physical IP standard cells, I/Os, memories and the Power Management Kit for the CMOS11LP process.

Further, Synopsys said its low power reference flow takes chip designers through each step of the design process to optimize and implement highly complex 45-nm low power designs and allows engineers to express low power design intent using UPF, while supporting detailed implementation and analysis with a full suite of tools from the Galaxy Design Platform, including Design Compiler synthesis, IC Compiler physical design, DFT MAX scan compression, Formality equivalency checking, Star-RCXT extraction, and PrimeTime signoff.

The reference flow is meant to automate and simplify the adoption of advanced low power technologies and techniques including concurrent multi-corner multi-mode (MCMM) analysis and optimization, multi-threshold CMOS (MTCMOS) power gating, multi-threshold leakage optimization, power-aware placement and clock tree synthesis, and power-aware test techniques, Synopsys added.